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SL4049B 参数 Datasheet PDF下载

SL4049B图片预览
型号: SL4049B
PDF下载: 下载PDF文件 查看货源
内容描述: 六角缓冲器/转换器 [Hex Buffer/Converter]
分类和应用: 转换器
文件页数/大小: 4 页 / 36 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
 浏览型号SL4049B的Datasheet PDF文件第1页浏览型号SL4049B的Datasheet PDF文件第3页浏览型号SL4049B的Datasheet PDF文件第4页  
SL4049B  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
VCC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
-0.5 to +20  
**  
V
IN  
VCC to +18  
V
VOUT  
IIN  
-0.5 to VCC +0.5  
V
±10  
mA  
mW  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
PD  
Tstg  
TL  
Power Dissipation per Output Transistor  
Storage Temperature  
100  
-65 to +150  
260  
mW  
°C  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SOIC Package)  
°C  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
The IW4049UB has high-to-low level voltage conversion capability but not low-to-high level; therefore it is  
**  
recommended that V ³ VCC  
IN  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
Min  
3.0  
Max  
18  
Unit  
V
**  
V
IN  
VCC  
0
18  
V
VOUT  
TA  
VCC  
+125  
V
-55  
°C  
**  
The SL4049B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is  
recommended that V ³ VCC  
IN  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range  
IN  
GND£(V or VOUT)£VCC.  
IN  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).  
CC  
Unused outputs must be left open.  
System Logic  
SLS  
Semiconductor