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ST8024T 参数 Datasheet PDF下载

ST8024T图片预览
型号: ST8024T
PDF下载: 下载PDF文件 查看货源
内容描述: COM / SEG LCD驱动 [COM/SEG LCD Driver]
分类和应用: 驱动
文件页数/大小: 28 页 / 641 K
品牌: SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
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ST8024T  
11.2  
AC Characteristics  
(Segment Mode 1) (LGND=VSS = GND = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C)  
PARAMETER SYMBOL CONDITIONS MIN TYP. MAX. UNIT NOTE  
Shift clock period  
tWCK  
tWCKH  
tWCKL  
tDS  
tDH  
tWLPH  
tLD  
tSL  
tLS  
tLH  
tS  
tR  
tF  
tSD  
tWDL  
tD  
tR,tF 10ns  
66  
23  
23  
15  
23  
30  
0
50  
30  
30  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
µs  
µs  
1
Shift clock "H" pulse width  
Shift clock "L" pulse width  
Data setup time  
Data hold time  
Latch pulse "H" pulse width  
Shift clock rise to latch pulse rise time  
Shift clock fall to latch pulse fall time  
Latch pulse rise to shift clock rise time  
Latch pulse fall to shift clock fall time  
Enable setup time  
Input signal rise time  
Input signal fall time  
/DISPOFF removal time  
/DISPOFF "L" pulse width  
Output delay time (1)  
50  
50  
2
2
100  
1.2  
CL = 15 pF  
CL = 15 pF  
CL = 15 pF  
41  
1.2  
1.2  
Output delay time (2)  
Output delay time (3)  
tPD1, tPD2  
tPD3  
NOTES:  
1. Takes the cascade connection into consideration.  
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.  
(Segment Mode 2) (LGND=VSS =GND = 0V, VDD = +3.0 ~ +4.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C)  
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE  
Shift clock period  
tWCK  
tWCKH  
tWCKL  
tDS  
tDH  
tWLPH  
tLD  
tSL  
tLS  
tLH  
tS  
tR  
tF  
tSD  
tWDL  
tD  
tR,tF 10ns  
82  
28  
28  
20  
23  
30  
0
65  
30  
30  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
µs  
µs  
1
Shift clock "H" pulse width  
Shift clock "L” pulse width  
Data setup time  
Data hold time  
Latch pulse "H" pulse width  
Shift clock rise to latch pulse rise time  
Shift clock fall to latch pulse fall time  
Latch pulse rise to shift clock rise time  
Latch pulse fall to shift clock fall time  
Enable setup time  
Input signal rise time  
Input signal fall time  
/DISPOFF removal time  
/DISPOFF "L" pulse width  
Output delay time (1)  
50  
50  
2
2
100  
1.2  
CL = 15 pF  
CL = 15 pF  
CL = 15 pF  
57  
1.2  
1.2  
Output delay time (2)  
Output delay time (3)  
tPD1, tPD2  
tPD3  
NOTES:  
1. Takes the cascade connection into consideration.  
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.  
Preliminary Ver 0.12  
Page 18/26  
2008/01/24  
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