ST7669V
7.7 POWER LEVEL DEFINITION
7.7.1 Power ON/OFF SEQUENCE
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 200msec after /RST
has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDDA can be powered down minimum
0msec after /RST has been released.
/CS can be applied at any timing or can be permanently grounded. /RST has priority over /CS.
There will be no damage to the display module if the power sequences are not met.
There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep
Out command. Also between receiving Sleep In command and Power Off Sequence.
If /RST line is not held stable by host during Power On Sequence as defined in Sections case1 and case2, then it will be
necessary to apply a Hardware Reset (/RST) after Host Power On Sequence is complete to ensure correct operation.
Otherwise function is not guaranteed. The power on/off sequence is illustrated below:
Case 1 – /RST line is held High or Unstable by Host at Power On
If /RST line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDDA
and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this
hardware reset.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
Ver 1.3
43/208
6/4/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
