ST7669V
(VSS=0V, VDDI= 2.8V, VDDA=2.4V to 3.3V, Ta = 25°C)
MIN MAX Unit Description
Signal
Symbol
Parameter
Address setup time
TAST
TAHT
TCHW
TCS
TCSH
TRCS
TRCSFM
TCSF
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
10
10
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0
-
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select hold time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
30
10
60
60
10
100
50
50
140
20
60
160
50
60
30
10
-
/CS
/WR
/RD (ID)
/RD (FM)
When read ID data
When read from frame
memory
TRDHFM Control pulse “H” duration (FM)
TRDLFM
TDST
TDHT
TRATFM
TODH
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (FM)
Output disable time
-
-
For maximum CL=30pF
For minimum CL=8pF
D[17:0]
340
80
10
Figure 7.10.2-2 Rising and Falling timing for Input and Output signal
Figure 7.10.2-3 Chip selection (/CS) timing
Ver 1.3
183/208
6/4/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
