ST7636R
5. BLOCK DIAGRAM
SEG0 TO SEG395 COM0 TO COM131
VDD1
VDD
V0 In
V1
COMMON
SEGMENT DRIVERS
V2
CSEL
V3
DRIVERS
V4
VSS
DATA LATCHES
COMMON
OUTPUT
V/F
CONTROLLER
CIRCUIT
Circuit
FRC/PWM FUNCTION
CIRCUIT
V0 out
RESET
VREF
CL
V/R
VR
Circuit
OSCILLATOR
CLS
DISPLAY DATA RAM
(DDRAM)
INTRS
TIMING
GENERATOR
[132X132X16]
VLCDin
VLCDout
DISPLAY
ADDRESS
COUNTER
Cap1N
Cap2P
Cap2N
Cap3P
Cap4P
Cap5P
Cap6P
Cap7P
V/C
ADDRESS COUNTER
Circuit
EEPROM
INSTRUCTION
VDD2
DATA
REGISTER
REGISTER
VDD3
VDD4
VDD5
BUS
INSTRUCTION
DECODER
HOLDER
VSS
MPU INTERFACE(PARALLEL & SERIAL)
Ver 1.4
13/109
2006/09/06