ST7628
12. RESET TIMING
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25°C)
Rating
Item
Signal
Symbol
Condition
Units
us
Min.
Max.
—
Reset “L” pulse width
/RST tRW
10
5
—
—
ms
(*note 5)
120
Reset time
tRT
ms
(*note 6,7)
Notes:
1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from EEPROM (or
similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a
rising edge of RST
2. Spike due to an electrostatic discharge on RST line does not cause irregular system reset according to the table
below:
RST Pulse
Shorter than 5µs
Longer than 9µs
Between 5µs and 9µs
Action
Reset Rejected
Reset
Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum
time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then
return to Default condition for Hardware Reset.
4. Spike Rejection also applies during a valid reset pulse as shown below:
Ver 1.4
197/213
2008/08
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
