ST7628
6.3 SYSTEM CONTROL
Name
I/O
Description
Reserved for testing only.
Please fix this pin to VDD.
CLS
I
CL
I/O
I
Reserved for testing only. Leave this pin open.
This PIN should connect to VDD.
CSEL
TCAP
VREF
I/O
O
Test pin. Left it opens.
Reference voltage output for monitor only. Left it opened.
When writing OTP, it needs external power supply voltage 7.5V~7.75V (>4mA) input to write
successfully.
VPP
I
6.4 MICROPROCESSOR INTERFACE
Name
I/O
Description
Reset input pin, when RST is “L”, initialization is executed.
Parallel / Serial data input select input
RST
I
IF3
H
H
H
H
L
IF2
H
H
L
IF1
H
L
MPU interface type
80 series 16-bit parallel
80 series 8-bit parallel
68 series 16-bit parallel
68 series 8-bit parallel
8-bit serial (4 line)
H
L
IF[3:1]
I
L
H
H
H
L
L
9-bit serial (3 line)
Note:
1. When fixing IF2=H & IF1=L, IF3 can be defined as parallel/Serial selection pin.
IF3=H: Parallel interface(80 8-bit); IF3=L:Serial interface(3-line)
2. Refer to Table 7.1.1. for detail interface connections.
Chip select input pins
/CS
A0
I
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15
become high impedance.
Register select input pin
A0 = "H": D0 to D15 or SI are display data
A0 = "L": D0 to D15 or SI are control command
In 3-line/4-line interface this pad will be used for SCL function
Ver 1.4
13/213
2008/08
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
