ST7586S
PIN DESCRIPTION
Power System
Name
Type
Description
VDD1
Power
VDD1 is the power of interface I/O circuit.
VDD2 is the analog power for internal booster. VDD3~5 are the analog power for LCD driver.
VDD2~5 and VDDX are separated in ITO and connected together by FPC or PCB.
Digital power for OSC circuit.
VDD2~5
VDDX
VSS1
Power
Power
Power
Power
Power
VDD2~5 and VDDX are separated in ITO and connected together by FPC or PCB.
Ground of interface, logic (VSS1) and OSC (VSSX) circuits.
Ground system should be connected together by FPC or PCB.
Ground of booster (VSS2) and LCD (VSS4) driver.
VSS2
VSS4
Ground system should be connected together by FPC or PCB.
Ground of OSC circuit.
VSSX
Ground system should be connected together by FPC or PCB.
Digital power source selection.
VD1S = “L”: the power source of digital circuit is VDD1.
VD1S = “H”: the power source of digital circuit is internal regulator.
VDD1 (TYP.) Cap. of VD1 and VSS
Level of VD1S
VSS1
VD1S
Input
1.8
2.8
3.0
3.3
Unnecessary
Necessary
Necessary
Necessary
VDD1
VDD1
VDD1
VD1I
VD1I is the power source of digital circuits.
Power
VD1O
VD1O is the VD1 output. VD1I and VD1O should be connected together by FPC or PCB.
Positive operating voltage of COM-drivers.
V0O
V0I
Power
Power
Input
V0O is the output of the positive Vop generator.
V0I is the positive Vop supply of LCD drivers.
V0S
V0S is the sensor of the positive Vop generator.
V0O, V0I & V0S should be separated on ITO and be connected together by FPC.
Negative operating voltage of COM-drivers.
XV0O
XV0I
Power
Power
Input
XV0O is the output of the negative Vop generator.
XV0I is the negative Vop supply of LCD drivers.
XV0S
XV0S is the sensor of the negative Vop generator.
XV0O, XV0I & XV0S should be separated on ITO and be connected together by FPC.
VG is the power of SEG-drivers. VM is the non-select voltage level of COM-drivers.
VGO is the output of the VG regulator.
VGI is the supply of SEG-drivers.
VGS is the sensor of the VG regulator.
VGO
VGI
VGS
VM
Power
Power
Input
VGO, VGI & VGS should be separated on ITO and be connected together by FPC.
Be sure the relationships (as shown below) among the LCD driving voltages:
V0 ≥ VG ≥ VM ≥ VSS ≥ XV0; VDDA-0.7 ≥ VM ≥ 0.9V; and 2*VDDA-0.7 ≥ VG ≥ 1.8V
When this IC is operating, VG and VM are generated according to the bias setting shown below:
Power
LCD Bias
VG
VM
1/N Bias
(2/N) x V0
(1/N) x V0
Note: N = 9~14
Ver-1.1a
12/63
2009/11/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
