ST7567
Power System Pins
Pin Name
VDD1
VDD2
VDD3
VSS1
Type
Description
No. of Pins
Power
Power
Power
Power
Power
Power
Digital power. If VDD1=VDD2, connect to VDD2 externally.
Analog power. If VDD1=VDD2, connect to VDD1 externally.
Power for reference voltage circuit.
3
4
2
2
3
1
Digital ground. Connect to VSS2 externally.
VSS2
Analog ground. Connect to VSS1 externally.
VSS3
Ground for reference voltage circuit.
V0 is the LCD driving voltage for common circuits at negative frame.
V0out is the output of V0 regulator. V0s is the feedback of V0 regulator.
V0in is the V0 input of common circuits.
V0out
V0in
V0s
2
2
1
Power
Power
Be sure that: V0 ≥ VG > VM > VSS ≥ XV0 (under operation).
V0out, V0in & V0s should be separated in ITO layout.
V0out, V0in & V0s should be connected together in FPC layout.
XV0 is the LCD driving voltage for common circuits at positive frame.
XV0out is the output of XV0 regulator. XV0s is the feedback of XV0 regulator.
XV0in is the V0 input of common circuits.
XV0out
XV0in
XV0s
2
2
1
XV0out, XV0in & XV0s should be separated in ITO layout.
XV0out, XV0in & XV0s should be connected together in FPC layout.
VG is the LCD driving voltage for segment circuits.
Vgout is the output of VG regulator. VGs is the feedback of VG regulator.
Vgin is the VG input of segment circuits.
VGout
Vgin
1
2
1
Power
Power
Vgout, Vgin & VGs should be separated in ITO layout.
Vgout, Vgin & VGs should be connected together in FPC layout.
1.6 ≤ VG < VDD2.
VGs
VM is the LCD driving voltage for common circuits.
0.8V ≤ VM < VDD2.
VMO
2
Test Pins
Pin Name
Type
T
Description
Test pin for power system.
No. of Pins
1
Vref
T1~T8
TFCOM
CL
This pin must be left open (without any kinds of connection).
Do NOT use. Reserved for testing.
Must be floating.
T
T
T
8
1
1
Do NOT use. Reserved for testing.
Must be floating.
Do NOT use. Reserved for testing.
Must be floating.
Ver 1.4b
10/49
2009/02/04
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
