VDM
R
R
RL = 27Ω
S1
D
OUT
VOD
D
GENERATOR
(NOTE 1)
50Ω
CL
= 15pF
(NOTE 2)
VOC
VCC
VCC
V
OH + VOL
VOM
=
1.5V
2
Figure 1. Driver DC Test Load Circuit
Figure 2. Driver Propagation Delay Test Circuit
S1
D
OUT
RL = 110Ω
CL
RL =
60Ω
OUT
D
C
L
= 50pF
(NOTE 2)
GENERATOR
(NOTE 1)
GENERATOR
(NOTE 1)
50Ω
50Ω
VCC
CL = 15pF (NOTE 2)
V
OH + VOL
VOM
=
1.5V
2
Figure 4. Driver Enable and Disable Timing Circuit,
Output HIGH
Figure 3. Driver Differential Output Delay and Transition
Time Circuit
VCC
OUT
R
L
= 110Ω
VID
R
S1
GENERATOR
(NOTE 1)
50Ω
0V OR 3V
D
OUT
C
L
= 15pF
(NOTE 2)
C
L
= 50pF
(NOTE 2)
GENERATOR
(NOTE 1)
50Ω
1.5V
0V
V
OM = VCC
2
Figure 6. Receiver Propagation Delay Test Circuit
Figure 5. Driver Enable and Disable Timing Circuit,
Output LOW
S1
S3
1.5V
VCC
1k
-1.5V
VID
R
S2
CL = 15pF
(NOTE 2)
GENERATOR
(NOTE 1)
50Ω
Figure 7. Receiver Enable and Disable Timing Circuit
Date: 6/23/04
SP3483 Low Power Slew Rate Limited Half-Duplex RS485 Transceivers
© Copyright 2004 Sipex Corporation
5
SIPEX [ SIPEX CORPORATION ]
