In applications that are sensitive to power-sup-
ply noise, decouple VCC to ground with a capaci-
tor of the same value as charge-pump capacitor
C1. Physically connect bypass capacitors as
close to the IC as possible.
Receivers
The receivers convert EIA/TIA-232 levels to
TTL or CMOS logic output levels. The
SP3222EB receivers have an inverting tri-state
output. Thesereceiveroutputs(RxOUT)aretri-
stated when the enable control EN = HIGH. In
the shutdown mode, the receivers can be active
or inactive. EN has no effect on TxOUT. The
truth table logic of the SP3222EB driver and
receiver outputs can be found in Table 2.
The charge pumps operate in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pumps are enabled. If the output voltage
exceed a magnitude of 5.5V, the charge pumps
are disabled. This oscillator controls the four
phases of the voltage shifting. A description of
each phase follows.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
haveatypicalhysteresismarginof300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, a 5kΩ pulldown resistor to ground
will commit the output of the receiver to a HIGH
state.
Phase 1
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is
–
transferred to C2 . Since C2+ is connected to
VCC, the voltage potential across capacitor C2
is now 2 times VCC.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach com-
paredtoolderless–efficientdesigns. Thecharge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated
dual charge pump that provides output voltages
5.5V regardless of the input voltage (VCC) over
the +3.0V to +5.5V range.
Phase 2
— VSS transfer — Phase two of the clock con-
nects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to GND. This transfers a negative generated
voltage to C3. This generated voltage is regu-
lated to a minimum voltage of -5.5V. Simulta-
neous with the transfer of the voltage to C3, the
positive side of capacitor C1 is switched to VCC
and the negative side is connected to GND.
In most circumstances, decoupling the power
supplycanbeachievedadequatelyusinga0.1µF
bypasscapacitoratC5(refertoFigures8and9).
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –VCC in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at VCC, the
voltage potential across C2 is 2 times VCC.
SHDN
EN
0
TxOUT
Tri-state
Tri-state
Active
RxOUT
Active
0
0
1
1
1
Tri-state
Active
Phase 4
0
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to GND,
and transfers this positive generated voltage
across C2 to C4, the VDD storage capacitor.
1
Active
Tri-state
Table 2. SP3222EB Truth Table Logic for Shutdown
and Enable Control
Rev. A Date:12/11/03
SP3222EB/3232EB True +3.0 to +5.5V RS-232 Transceivers
© Copyright 2003 Sipex Corporation
10
SIPEX [ SIPEX CORPORATION ]
