TIMING CHARACTERISTICS
(Typical @ 25°C with VDD = +5V, unless otherwise noted)
PARAMETER
MIN.
8.25
400
TYP.
MAX
.UNIT
µs
COND.
Thoughput Time (tTP=tA+tC)
Acquisition Time (tA) (2 SCLK Periods)
Conversion Time (tC) (31 SCLK Periods)
SCLK Low Pulse Width (tSKL)
500
ns
7.75
110
110
250
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
125
125
SCLK High Pulse Width (tSKH)
SCLK Period (tSKT)
Buss Access Time (tCBA)
51
45
Buss Relinquish Time (tBR)
Setup Time -SCLK Falling to CSN Falling (tCSSU)
CSN Low Before SCLK Rises (tCS)
SCLK Falling to Data Valid (tSD)
CSN Falling to status Rising (tDCS)
SCLK 33 Falling to Status Rising Free Run (tDSS)
SCLK32 Falling to Status Falling ( tDSE)
Delay SD Low to initiate Conversion (tpu)
Aperture Delay Slave-Mode (tAPC)
Aperture Delay Free-Running Mode (tAPS)
0
90
50
69
70
45
5
30
35
TM
SP8530DS/01
SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter
© Copyright 2000 Sipex Corporation
8
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