U62H1708
Read Cycle 1: Ai-controlled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Output Data Valid
Previous Data Valid
tv(A)
Output
Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
ten(E)
tsu(A)
E1
tdis(E)
tdis(E)
ta(E)
tsu(A)
ten(E)
E2
G
ta(G)
tdis(G)
ten(G)
High-Z
DQi
Output Data Valid
*
Output
tPU
*
tPD
ICC(OP)
ICC(SB)
50 %
50 %
* The same applies to E1
Write Cycle1: W-controlled
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
tsu(E)
tw(W)
tsu(D)
E2
W
tsu(A)
th(D)
DQi
Input Data Valid
tdis(W)
Input
ten(W)
High-Z
DQi
Output
G
8
April 21, 2004
SIMTEK [ SIMTEK CORPORATION ]
