STK15C88
PIN CONFIGURATIONS
A14
1
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A12
A7
2
W
A13
A8
3
A6
A5
A4
A3
4
5
A9
A11
6
(TOP)
7
G
A10
A2
8
A1
A0
E
9
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
13
14
DQ0
DQ1
DQ2
VSS
28 Pin 300 mil SOIC
28 Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, +10%
Ground
CC
SS
Rev 2.0
Document Control #ML0016
Jan, 2008
2
SIMTEK [ SIMTEK CORPORATION ]
