STK15C88-3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)
SYMBOLS
STK15C88-3-35
STK15C88-3-45
STK15C88-3-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
40
40
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
25
0
30
0
40
0
AVWH
AVEH
AW
t
t
t
AVWL
AVEL
EHAX
AS
t
t
t
0
0
0
WHAX
WR
h, i
t
t
13
15
20
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
W
t
WLWH
15
16
t
t
DVWH
WHDX
DATA IN
DATA VALID
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
t
AVAV
ADDRESS
18
14
19
t
t
AVEL
ELEH
t
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
DVEH
t
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
September 2002
4