STK15C88
SRAM READ CYCLES #1 & #2 (V = 5.0V 10%)
CC
SYMBOLS
STK15C88-25 STK15C88-45
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
25
45
AVAV
RC
AA
g
3
Address Access Time
Output Enable to Data Valid
25
10
45
20
AVQV
4
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
g
h
h
5
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
5
5
5
5
6
7
10
10
25
15
15
45
HZ
8
0
0
0
0
OLZ
OHZ
PA
9
GHQZ
e
d
10
11
ELICCH
EHICCL
,
e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
f
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
E
1
ELQV
11
EHICCL
t
t
6
ELQX
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 0.3
Document Control #ML0016
February, 2007
4
SIMTEK [ SIMTEK CORPORATION ]
