Preliminary
STK14EC8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK14EC8-15
STK14EC8-25
STK14EC8-45
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
15
25
45
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
c
c
t
t
15
25
45
AVAV
ELEH
AVQV
d
d
Address Access Time
15
10
25
12
45
20
AVQV
Output Enable to Data Valid
Output Hold after Address Change
GLQV
AXQX
ELQX
OE
OH
LZ
d
d
e
e
t
3
3
3
3
3
3
AXQX
Address Change or Chip Enable to
Output Active
ns
ns
7
t
t
Address Change or Chip Disable to
Output Inactive
EHQZ
HZ
7
10
15
8
9
t
t
t
t
t
t
t
t
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
0
0
0
0
ns
ns
ns
ns
GLQX
OLZ
OHZ
PA
7
10
25
15
45
GHQZ
b
b
10
11
ELICCH
EHICCL
15
PS
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low
Note e: Measured ± 200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
c,d,f
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
c,f
SRAM READ CYCLE #2: E and G Controlled
ADDRESS
2
29
tE LE H
tEHAX
1
11
tEL Q V
tEHI CC L
6
E
tELQ X
27
7
tEHQ Z
3
tAV QV
G
9
4
tG L QV
tGH Q Z
8
tG L Q X
DQ (DATA OUT)
DATA VAL ID
10
tELI CC H
AC TIVE
STAND BY
ICC
Rev 1.1
Document Control #ML0060
Jan, 2008
5
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
