Preliminary
STK14EC16
After the t
cycle time, the SRAM will once
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently
(program bugs, incoming inspection routines,
etc.).
RECALL
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.Care must be taken so
the controlling falling edge is glitch and ring free so
as not to double clock the read address.
DATA PROTECTION
The STK14EC16 protects data from corruption dur-
ing low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
• The autostore enabled/disabled feature will reset
to “autostore enabled” on every power down
event captured by the nvSRAM. The application
firmware should disable autostore on each reset
sequence that this behavior is desired.
voltage condition is detected when V <V
.
CC
SWITCH
If the STK14EC16 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
• The V
value specified in this datasheet
cap
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max V
value because the nvSRAM
cap
internal algorithm calculates V
charge time
cap
based on this max Vcap value. Customers that
want to use a larger V value to make sure
cap
NOISE CONSIDERATIONS
The STK14EC16 is a high-speed memory and so
must have a high-frequency bypass capacitor of 0.1
there is extra store charge and store time should
discuss their V size selection with Simtek to
cap
understand any impact on the V
voltage level
cap
µF connected between both V
pins and V
CC
SS
at the end of a t
period.
RECALL
ground plane with no plane break to chip V . Use
SS
leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of
power, ground, and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14EC16 with
the benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the prod-
uct’s main system values, experience gained work-
ing with hundreds of applications has resulted in the
following suggestions as best practices:
shows the relationship between I
and READ/
CC
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
V
=3.6V, and chip enable at maximum frequency.
CC
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14EC16 depends on the following items:
• The non-volatile cells in this nvSRAM product are
delivered from Simtek with 0x00 written in all
cells. Incoming inspection routines at customer or
contract manufacturer’s sites will sometimes
reprogram these values. Final NV patterns are
typically complex 4-byte pattern of 46 E6 49 53
hex or more random bytes. End product’s firm-
ware should not assume an NV array is in a set
programmed state. Routines that check memory
content values to determine first time system con-
figuration, cold or warm boot status, etc. should
always program a unique NV pattern (i.e., repeat-
ing 4-byte pattern of 46 E6 49 53 hex) as part of
the final system manufacturing test to ensure
these system routines work consistently.
1
2
3
4
5
6
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The VCC Level
I/O Loading
Rev 1.1
Document Control #ML0061
Jan, 2008
14
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
