Preliminary
STK14EC16
is tri-state during power up. Many MPU’s will tri-state
their controls on power up. This should be verified
when using the pullup. When the nvSRAM comes
out on power-on-recall, the MPU must be active or
the W held inactive until the MPU comes out of
reset.
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14EC16 software STORE cycle is initiated
by executing sequential E controlled or G controlled
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are dis-
abled until the cycle is completed.
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are per-
formed regardless of whether a WRITE operation
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x8FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK14EC16 provides the HSB pin for control-
ling and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14EC8 will conditionally initiate a STORE oper-
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence and that G, UB, and LB are active. After
ation after t
. An actual STORE cycle will only
DELAY
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
the t
cycle time has been fulfilled, the SRAM
STORE
will again be activated for READ and WRITE opera-
tion.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14EC16 will
SOFTWARE RECALL
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
1 Read Address 0x4E38 Valid READ
continue to allow SRAM operations for t
. Dur-
DELAY
ing t
, multiple SRAM READ operations may
DELAY
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, t , to com-
plete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until
HSB returns high.
DELAY
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x4C63 Initiate RECALL Cycle
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V <V
), an internal RECALL request will be
CC
SWITCH
latched. When V
voltage of V
cally be initiated and will take t
once again exceeds the sense
, a RECALL cycle will automati-
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
CC
SWITCH
to complete.
HRECALL
13
Simtek Confidential
Rev 1.1
Document Control #ML0061
Jan, 2008