STK14D88
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address 0x0E38 Valid READ
2 Read Address 0x31C7 Valid READ
3 Read Address 0x03E0 Valid READ
4 Read Address 0x3C1F Valid READ
5 Read Address 0x303F Valid READ
6 Read Address 0x0FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK14D88 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14D88 will conditionally initiate a STORE oper-
ation after t
. An actual STORE cycle will only
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
DELAY
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also
acts as an open drain driver that is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin
should be externally pulled up if it is used to drive
other inputs.
sequence. After the t
cycle time has been ful-
STORE
filled, the SRAM will again be activated for READ
and WRITE operation.
SOFTWARE RECALL
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14D88 will
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled READ
operations must be performed:
continue SRAM operations for t
. During t
,
DELAY
DELAY
multiple SRAM READ operations may take place. If
a WRITE is in progress when HSB is pulled low, it
will be allowed a time, t
, to complete. However,
DELAY
any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
1 Read Address 0x0E38 Valid READ
2 Read Address 0x31C7 Valid READ
3 Read Address 0x03E0 Valid READ
4 Read Address 0x3C1F Valid READ
5 Read Address 0x303F Valid READ
6 Read Address 0x0C63 Initiate RECALL Cycle
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V <V
), an internal RECALL request will be
CC
SWITCH
latched. When V
once again exceeds the sense
, a RECALL cycle will automati-
CC
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
voltage of V
SWITCH
cally be initiated and will take t
to complete.
HRECALL
After the t
cycle time, the SRAM will once
RECALL
SOFTWARE STORE
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14D88 software STORE cycle is initiated
by executing sequential E controlled READ cycles
from six specific address locations in exact order.
During the STORE cycle, previous data is erased
and then the new data is programmed into the non-
volatile elements. Once a STORE cycle is initiated,
further memory inputs and outputs are disabled until
the cycle is completed.
Rev 1.7
Document Control #ML0033
February 2007
12
SIMTEK [ SIMTEK CORPORATION ]
