STK14CA8
against events that might flip the bit inadvertently
(program bugs, incoming inspection routines,
etc.).
DATA PROTECTION
The STK14CA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
• If autostore has been firmware disabled, it will not
reset to “autostore enabled” on every power
down event captured by the nvSRAM. The appli-
cation firmware should re-enable or re-disable
autostore on each reset sequence based on the
behavior desired.
voltage condition is detected when V <V
.
CC
SWITCH
If the STK14CA8 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
• The V
value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
cap
NOISE CONSIDERATIONS
exceed the max V
value because the nvSRAM
cap
internal algorithm calculates V
charge time
The STK14CA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
cap
based on this max Vcap value. Customers that
want to use a larger V value to make sure
approximately 0.1 µF connected between V
and
cap
CC
there is extra store charge and store time should
discuss their V size selection with Simtek to
V
, using leads and traces that are a short as pos-
SS
sible. As with all high-speed CMOS ICs, careful
routing of power, ground, and signals will reduce cir-
cuit noise.
cap
understand any impact on the V
voltage level
cap
at the end of a t
period.
RECALL
LOW AVERAGE ACTIVE POWER
BEST PRACTICES
CMOS technology provides the STK14CA8 with the
benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the prod-
uct’s main system values, experience gained work-
ing with hundreds of applications has resulted in the
following suggestions as best practices:
shows the relationship between I
and READ/
CC
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
• The non-volatile cells in an nvSRAM are pro-
grammed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV pat-
terns are typically repeating patterns of AA, 55,
00, FF, A5, or 5A. End product’s firmware should
not assume an NV array is in a set programmed
state. Routines that check memory content val-
ues to determine first time system configuration,
cold or warm boot status, etc. should always pro-
gram a unique NV pattern (e.g., complex 4-byte
pattern of 46 E6 49 53 hex or more random
bytes) as part of the final system manufacturing
test to ensure these system routines work consis-
tently.
V
=3.6V, and chip enable at maximum frequency.
CC
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14CA8 depends on the following items:
1
2
3
4
5
6
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The VCC Level
I/O Loading
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
Rev 2.1
Document Control #ML0022
Jan, 2008
13
SIMTEK [ SIMTEK CORPORATION ]
