STK14CA8
LOW AVERAGE ACTIVE POWER
DATA PROTECTION
The STK14CA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
CMOS technology provides the STK14CA8 with the
benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
voltage condition is detected when V <V
.
CC
SWITCH
shows the relationship between I
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
and READ/
CC
If the STK14CA8 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
V
=3.6V, and chip enable at maximum frequency.
CC
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14CA8 depends on the following items:
NOISE CONSIDERATIONS
1
2
3
4
5
6
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The VCC Level
The STK14CA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1 μF connected between V
and
CC
V
, using leads and traces that are a short as pos-
SS
sible. As with all high-speed CMOS ICs, careful
routing of power, ground, and signals will reduce cir-
cuit noise.
I/O Loading
Figure 4 - Current vs Cycle Time
Rev 1.5
Document Control #ML0022
February 2007
13
SIMTEK [ SIMTEK CORPORATION ]
