STK14CA8
MODE SELECTION
E
W
G
A -A
Mode
I/O
Power
Notes
15
0
H
L
L
X
H
L
X
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
X
Active
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
q,r,s
q,r,s
q,r,s
q,r,s
L
L
L
H
H
H
H
L
L
L
L
Active
AutoStore Disable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Active
AutoStore Enable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
I
CC2
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
Active
Nonvolatile Recall
Notes
q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
r: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
s: I/O state depends on the state of G. The I/O table shown assumes G low
Rev 1.5
Document Control #ML0022
February 2007
10