STK14CA8
PACKAGES
VCAP
A16
A14
1
2
VCC
A15
HSB
48
47
VCAP
A16
A14
1
2
3
4
5
6
VCC
A15
32
31
3
4
5
6
HSB
W
A13
A8
30
29
28
27
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A12
A7
A6
A12
A7
A6
A5
W
A13
A8
A5
A4
A3
A2
A1
A9
7
8
9
10
11
12
13
14
15
16
26
25
24
23
22
21
20
19
18
17
7
8
9
10
11
12
13
14
15
16
A9
A11
G
A10
E
DQ7
A4
A11
A0
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
VSS
VSS
DQ0
A3
A2
A1
A0
DQ6
G
A10
E
DQ7
DQ5
DQ4
DQ3
VCC
32 Pin SOIC
17
18
32
31
30
29
28
27
26
25
19
20
21
22
23
24
DQ1
DQ2
Relative PCB area usage.
48 Pin SSOP
See website for detailed package
size specifications.
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
16
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 3.0V, +20%, -10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
Power Supply
No Connect
Ground
SS
(Blank)
Unlabeled pins have no internal connections.
Rev 1.5
Document Control #ML0022
February 2007
2
SIMTEK [ SIMTEK CORPORATION ]
