STK14CA8
nvSRAM OPERATION
nvSRAM
AutoStore OPERATION
The STK14CA8 nvSRAM is made up of two func-
tional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique archi-
tecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14CA8 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 200K STORE operations.
The STK14CA8 stores data to nvSRAM using one
of three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
QuanumTrap technology is enabled by default on
the STK14CA8.
During normal operation, the device will draw cur-
rent from V
to charge a capacitor connected to
CC
the V
pin. This stored charge will be used by the
CAP
chip to perform a single STORE operation. If the
voltage on the V pin drops below V , the
CC
SWITCH
part will automatically disconnect the V
pin from
CAP
V
. A STORE operation will be initiated with power
CC
SRAM READ
provided by the V
capacitor.
CAP
The STK14CA8 performs a READ cycle whenever
E and G are low while W and HSB are high. The
Figure 3 shows the proper connection of the storage
capacitor (V ) for automatic store operation.
CAP
address specified on pins A
determine which of
Refer to the DC CHARACTERISTICS table for the
size of V . The voltage on the V pin is driven
0-16
the 131,072 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
CAP
CAP
to 5V by a charge pump internal to the chip. A pull
up should be placed on W to hold it inactive during
power up.
puts will be valid after a delay of t
(READ cycle
AVQV
#1). If the READ is initiated by E and G, the outputs
will be valid at t or at t , whichever is later
ELQV
GLQV
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are per-
formed regardless of whether a WRITE operation
(READ cycle #2). The data outputs will repeatedly
respond to address changes within the t
AVQV
access time without the need for transitions on any
control input pins, and will remain valid until another
address change or until E or G is brought high, or W
and HSB is brought low.
SRAM WRITE
VCC
VCAP
VCC
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
W
DQ0-7 will be written into memory if it is valid t
DVWH
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
DVEH
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
low.
after W goes
WLQZ
Figure 3. AutoStore Mode
Rev 1.5
Document Control #ML0022
February 2007
11
SIMTEK [ SIMTEK CORPORATION ]
