STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
STK14CA8-25
STK14CA8-35
STK14CA8-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
tACS
MIN
MAX
MIN
MAX
MIN
MAX
tELQV
1
2
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c
c
tAVAV
tAVAV
tRC
tAA
tOE
tOH
tLZ
25
35
45
d
tAVQV
3
Address Access Time
25
12
35
15
45
20
tGLQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
d
tAXQX
5
3
3
3
3
3
3
tELQX
tEHQZ
tGLQX
6
e
tHZ
tOLZ
tOHZ
tPA
tPS
7
10
10
25
13
13
35
15
15
45
8
0
0
0
0
0
0
e
tGHQZ
9
b
tELICC
10
b
tEHICC
11
Notes
c:
W
must be high during SRAM READ cycles
and
d: Device is continuously selected with
E
G
both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledc,f
2
tAVAV
ADDRESS
1
tELQV
11
tEHICCL
6
tELQX
E
7
tEHQZ
G
9
tGHQZ
4
tGLQV
8
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ACTIVE
STANDBY
ICC
December 2004
5
Document Control #ML0022 rev 1.0