STK14CA8
HARDWARE STORE CYCLE
SYMBOLS
NO.
STK14CA8
PARAMETER
UNITS
NOTES
Standard
tDELAY
tHLHX
tHLBL
Alternate
MIN
MAX
tHLQZ
31
32
33
Time Allowed to Complete SRAM Cycle
Hardware STORE Pulse Width
1
µs
ns
ns
p
15
Hardware STORE Low to STORE Busy
300
Notes
p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
33
tHLBL
HSB (OUT)
HIGH IMPEDENCE
DATA VALID
HIGH IMPEDENCE
31
tDELAY
DQ (DATA OUT)
DATA VALID
December 2004
10
Document Control #ML0022 rev 1.0