STK14C88
e
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK14C88-25
STK14C88-35
STK14C88-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
Read Cycle Time
25
35
45
AVAV
h
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
h
i
5
5
5
5
5
5
5
6
7
10
10
25
13
13
35
15
15
45
HZ
8
0
0
0
0
0
0
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E and G < V and W > V ; device is continuously selected.
IL
IH
Note i: Measured 200mV from steady state output voltage.
g, h
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
g
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
1
ELQV
11
EHICCL
t
t
6
ELQX
E
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
GLQX
t
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 0.3
Document Control #ML0014
February, 2007
4
SIMTEK [ SIMTEK CORPORATION ]
