STK14C88
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
AutoStore INHIBIT MODE
If an automatic STORE on power loss is not
required, then VCC can be tied to ground and sys-
tem power applied to VCAP (Figure 2). This is the
AutoStore Inhibit Mode, in which the AutoStore func-
tion is disabled. If the STK14C88 is operated in this
configuration, references to VCC should be changed
to VCAP throughout this data sheet. In this mode,
STORE operations may be triggered through soft-
ware control. It is not permissible to change
between these three options “on the fly.”
The HSB pin can be used to synchronize multiple
STK14C88s while using a single larger capacitor. To
operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK14C88s. An external pull-up resistor to + 5V is
required since HSB acts as an open drain pull down.
The VCAP pins from the other STK14C88 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK14C88s detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request
a STORE cycle (a STORE will take place in those
STK14C88s that have been written since the last
nonvolatile cycle).
1
32
31
30
During any STORE operation, regardless of how it
was initiated, the STK14C88 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK14C88 will remain disabled until the HSB
pin returns high.
If HSB is not used, it should be left unconnected.
17
16
BEST PRACTICES
Figure 2: AutoStore Inhibit Mode
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the prod-
uct’s main system values, experience gained work-
ing with hundreds of applications has resulted in the
following suggestions as best practices:
HSB OPERATION
The STK14C88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK14C88 will
• The non-volatile cells in an nvSRAM are pro-
grammed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV pat-
terns are typically repeating patterns of AA, 55,
00, FF, A5, or 5A. End product’s firmware should
not assume an NV array is in a set programmed
state. Routines that check memory content val-
ues to determine first time system configuration,
cold or warm boot status, etc. should always pro-
gram a unique NV pattern (e.g., complex 4-byte
pattern of 46 E6 49 53 hex or more random
bytes) as part of the final system manufacturing
test to ensure these system routines work consis-
tently.
conditionally initiate a STORE operation after tDELAY
;
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive
pullup and is internally driven low to indicate a busy
condition while the STORE (initiated by any means)
is in progress. Pull up this pin with an external 10K
ohm resistor to VCAP if HSB is used as a driver.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14C88 will
continue SRAM operations for tDELAY. During tDELAY
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
,
Rev 2.0
Document Control #ML0014
Feb, 2008
11
SIMTEK [ SIMTEK CORPORATION ]
