STK14C88
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
I/O
Output High Z
Output Data
Input Data
POWER
Standby
NOTES
13
H
X
X
X
X
Not Selected
Read SRAM
Write SRAM
H
Active
Active
t
L
H
X
X
L
Nonvolatile STORE
Output High Z
lCC
2
m
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE
(VCC = 5.0V ± 10%)e
SYMBOLS
NO.
STK14C88
PARAMETER
UNITS NOTES
Standard
tSTORE
tDELAY
Alternate
MIN
MAX
22
23
24
25
26
tHLHZ
STORE Cycle Duration
10
ms
μs
ns
ns
ns
n
n
tHLQZ
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
tRECOVER
tHLHX
tHHQX
700
300
n, o
15
tHLBL
Hardware STORE Low to STORE Busy
Note n: E and G low and W high for output behavior.
Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
tHLHX
HSB (IN)
24
tRECOVER
22
tSTORE
26
tHLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
tDELAY
DQ (DATA OUT)
DATA VALID
Rev 2.0
Document Control #ML0014
Feb, 2008
6
SIMTEK [ SIMTEK CORPORATION ]
