STK14C88-3
parts can be tied together and share a single capac-
itor. The capacitor size must be scaled by the num-
ber of devices connected to it. When any one of the
STK14C88-3s detects a power loss and asserts
HSB, the common HSB pin will cause all parts to
request a STORE cycle (a STORE will take place in
those STK14C88-3s that have been written since
the last nonvolatile cycle).
If the chip enable duty cycle is less than 100%, only
standby current is drawn when the chip is disabled.
The overall average current drawn by the
STK14C88-3 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the duty cycle of chip
enable; 3) the overall cycle rate for accesses; 4) the
ratio of READs to WRITEs; 5) the operating tempera-
ture; 6) the V level; and 7) I/O loading.
cc
During any STORE operation, regardless of how it
was initiated, the STK14C88-3 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK14C88-3 will remain disabled until the HSB
pin returns high.
100
80
60
If HSB is not used, it should be left unconnected.
PREVENTING STORES
40
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20μs at the onset of a STORE. When
the STK14C88-3 is connected for AutoStore opera-
tion (system VCC connected to VCCX and a 68μF
capacitor on VCAP) and VCC crosses VSWITCH on the
way down, the STK14C88-3 will attempt to pull HSB
low; if HSB doesn’t actually get below VIL, the part
will stop trying to pull HSB low and abort the STORE
attempt.
TTL
20
CMOS
150 200
0
50
100
Cycle Time (ns)
Figure 5: Icc (max) Reads
100
80
HARDWARE PROTECT
60
The STK14C88-3 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs will be inhibited.
TTL
40
20
CMOS
LOW AVERAGE ACTIVE POWER
The STK14C88-3 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 3.6V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE cycles.
0
50
100
150
200
Cycle Time (ns)
Figure 6: Icc (max) Writes
Rev 0.6
Document Control #ML0015
February 2007
12
SIMTEK [ SIMTEK CORPORATION ]
