STK11C88
SRAM READ CYCLES #1 & #2
(V = 5.0V + 10%)
CC
SYMBOLS
NO.
STK11C88-25 STK11C88-45
UNITS
PARAMETER
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
45
AVAV
RC
AA
g
3
Address Access Time
Output Enable to Data Valid
25
10
45
20
AVQV
4
GLQV
OE
OH
LZ
g
5
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
15
15
45
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 0.3
Document Control #ML0012
February 2007
4
SIMTEK [ SIMTEK CORPORATION ]
