STK11C88
PIN CONFIGURATIONS
A14
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
VCC
A12
A7
A6
A5
A4
A3
W
A13
A8
5
6
7
8
A9
A11
G
A10
E
A2
A1
9
10
11
12
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
VSS
17
16
15
13
14
28 - Pin 300 mil SOIC
28 - Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
-A
I/O
Description
A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 0.3
Document Control #ML0012
February 2007
2
SIMTEK [ SIMTEK CORPORATION ]
