Si
I
2024
Fibre Channel Quad SerDes
REF_LOCK
Si
I
2024
10
Tx+
TxD
FIFO
Mux
Serializer
1.0625/2.125 Gbps
transmit signal
TBC
Mux
10
Tx
PLL
Sampler
Deserializer
Byte
Sync
Tx-
REFCLK
Tx_RATE
1.0625/2.125 Gbps
receive signal
EWRAP
COM_DET
Rx+
Rx-
10
RxD
Rx_LOS
SiI 2024 Features
Fibre Channel SerDes
Rx_RATE
RBC_SYNC
RBC[0:1]
Rx
PLL
General
TX_EMP_EN
• Fibre Channel-compliant
• Multi-rate: 1.0625 Gbps and
2.125 Gbps
• Four independent channels
• Advanced-power supply filtering
SSTL CTRL
VREFT
VREFR
TX_AMP
CTRL
TX_EMP_C
EN_CDET
JTAG CTRL
TMS
TRSTN
TDO
TDI
TCK
Low Power
• Single 1.8V supply for core circuits
and 2.5V supply for parallel I/O
• Power dissipation: 250 mW per
channel
Highly Reliable Serial
Interface
Cost Effective
• Standard CMOS technology
• Plastic 324-pin PBGA
• Individually selectable Tx and Rx
data rates per channel
• Selectable pre-emphasis control
• Selectable Tx swing control
• Low-transmit jitter design
• On-chip termination resistor
• MSL
TM
-based technology proven
with PanelLink
®
ICs for the PC and
CE markets (2-5 Gbps, over 30M
units shipped)
• Robust design for "noisy"
environments
Parallel I/O Interface
Proven Technology
• 10-bit interface with DDR for
2.125 Gbps mode
• Flexibility of using reference clock
(REFCLK) instead of transmit byte
clocks (TBC) in “noisy” environments
• Separate TBC for latching parallel
input data
• SSTL_2 and High-Speed Parallel
Interface (HSPI)-compliant
Part Number - SiI2024CB324
©2002 Silicon Image, Inc. All rights reserved. Silicon Image, the Silicon Image logo, MSL, SiI, SiI 2024, SATALink
and PanelLink are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other
countries. Product specifications are subject to change without notice. Printed in the U.S.A. 9/02 SiI-PB-0029
Silicon Image, Inc.
1060 E. Arques, Sunnyvale, CA 94085
T 408.616.4000 F 408.830.9530
www.siliconimage.com
SILICONIMAGE [ Silicon image ]
