SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Other Features
• Features independent 256-byte FIFOs (32-bit x 64 deep) per Serial ATA channel for host reads and writes.
• Supports legacy type operations (Master/Slave drive access) using I/O-mapped register space
• Supports 4 concurrent operations using memory-mapped register space
• Features Serial ATA to PCI interrupt masking.
• Features Watch Dog Timer for fault resiliency.
• Provides 8 bits of General Purpose I/O (GPIO)
Applications
• PC motherboards
• Serial ATA drive add on cards
• Serial ATA RAID cards
References
For more details about the Serial ATA technology, the reader is referred to the following industry specifications:
• Serial ATA / High Speed Serialized AT Attachment specification, Revision 1.0
• PCI Local Bus Specification Revision 2.3
• Advanced Power Management Specification Revision 1.0
• PCI IDE Controller Specification Revision 1.0
• Programming Interface for Bus Master IDE Controller, Revision 1.0
Functional Description
The SiI3114 is a PCI-to-Serial ATA controller chip that transfers data between the PCI bus and storage media (e.g
hard disk drive, etc). The SiI3114 consists of the following functional blocks:
• PCI Interface. Provides the interface to any system that has a PCI bus. Instructions and system clocks are
based on this interface.
• Serial ATA Interface. Four separate channels to access storage media such as hard disk drive, floppy disk
drive, CD-ROM.
PCI Interface
The SiI3114 PCI interface is compliant with the PCI Local Bus Specification (Revision 2.3). The SiI3114 can act as
a PCI master and a PCI slave, and contains the SiI3114 PCI configuration space and internal registers. When the
SiI3114 needs to access shared memory, it becomes the bus master of the PCI bus and completes the memory
cycle without external intervention. In the mode when it acts as a bridge between the PCI bus and the Serial ATA
bus it will behave as a PCI slave.
PCI Initialization
Generally, when a system initializes a module containing a PCI device, the configuration manager reads the
configuration space of each PCI device on the PCI bus. Hardware signals select a specific PCI device based on a
bus number, a slot number, and a function number. If a device that is addressed (via signal lines) responds to the
configuration cycle by claiming the bus, then that function's configuration space is read out from the device during
the cycle. Because any PCI device can be a multifunction device, every supported function's configuration space
needs to be read from the device. Based on the information read, the configuration manager will assign system
resources to each supported function within the device. Sometimes new information needs to be written into the
function's configuration space. This is accomplished with a configuration write cycle.
PCI Bus Operations
The SiI3114 behaves either as a PCI master or a PCI slave device at any time and switches between these
modes as required during device operation. As a PCI slave, the SiI3114 responds to the following PCI bus
operations:
• I/O Read
• I/O Write
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
SILICONIMAGE [ Silicon image ]
