SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Create a Physical Region Descriptor (PRD) Table.
A PRD table is an array where each entry describes the location and size of a physical memory buffer
that will be used during the DMA operation. Each PRD table entry is 64-bits in length, formatted as
follows; bits [31:0] contain the 32-bit starting address of the memory buffer, bits [47:32] contain the 16-bit
size of the memory buffer, bits [62:48] are normally unused, bit 63 flags the end of the PRD table and
therefore should only be set in the last entry of the PRD table. The PRD table itself must be constructed
in a memory region that can be directly accessed by the SiI3114 controller. Once the PRD table is built,
the controller must be informed of its location. This is accomplished by writing the 32-bit address of the
PRD table to the PRD Table Address – Channel x register.
Enable DMA transfer.
DMA is enabled by writing bits [7:0] of the PCI Bus Master – Channel x register. Bit 3 of this register
controls the direction of the DMA transfer; 1 = write to memory, 0 = read from memory. Setting bit 0 of the
register enables the controller to perform DMA operations.
Note: Task file registers are inaccessible as long as bit 0 is set.
Wait for a PCI interrupt.
When a PCI interrupt occurs, read the PCI Master – Channel x status register and check the DMA status
bits. The possible combinations of the status bits [18:16] are defined below.
000B = If the device does not report an error, then the PRD table specified a size that is smaller
than the transfer size.
001B = DMA transfer in progress.
010B = The controller had a problem transferring data to/from memory.
100B = Normal completion.
101B = If the device does not report an error, then the PRD specified a size that is larger than the
transfer size.
Make sure PCI bus master operation of the SiI3114 is stopped by clearing bit 0 of the PCI Bus Master –
Channel x register.
Note: The task file registers are not accessible as long as bit 0 is set. Clearing bit 0 causes bit 16 to be
cleared as well.
Read the device status at bits [13:24] in the Channel x Task File Register 1 register to clear the device
interrupt (and the PCI Interrupt) and determine if there was error.
Write ‘1’ to bit 18 (DMA Comp) in the PCI Bus Master – Channel x register to clear the status.
Virtual DMA Read/Write Operation
In virtual DMA operation the controller uses a PIO data transfer mode to move data between an ATA/ATAPI device
and the controller, and uses DMA to move that same data between the controller and the host memory. For
ATA/ATAPI devices that cannot operate in a “true” DMA mode, virtual DMA provides two benefits; first, using DMA
to move data reduces the demand on the host CPU, and second, systems that use virtual memory often require
that data buffers that will be accessed directly by low level device drivers be “mapped” into the operating system’s
address space, in virtual DMA mode the CPU does not access the data buffer directly, so the overhead of
obtaining the mapping to operating system address space is eliminated.
Using Virtual DMA with Non-DMA Capable Devices
Once the SiI3114 is initialized via the initialization sequence described in the “Recommended Initialization
Sequence for the SiI3114” section, and the ATA device has been initialized for PIO mode data transfer per the
guidelines in the “Serial ATA Device Initialization” section, virtual DMA read/write operations may be performed by
following the programming sequence described below.
Note: The watchdog timer feature is compatible with virtual DMA operation. See section 0 for details about using
the watchdog timer.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
