SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
• Bit [15:08]: Task File Cylinder High (R/W). This bit field defines the Channel X Task File Cylinder High
register.
• Bit [07:00]: Task File Cylinder Low (R/W). This bit field defines the Channel X Task File Cylinder Low
register.
Channel X Task File Register 2
Address Offset: 88H / C8H / 288H / 2C8H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device Control
Auxiliary Status
Reserved
Reserved
Reserved
This register defines one of the Channel X Task File registers in the SiI3114. Access to these bit fields is
permitted if the PCI bus Byte Enable is active for one byte only.
The register bits are defined below.
• Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [23:16]: Task File Device Control (W). This bit field defines the Channel X Task File Device Control
register.
• Bit [23:16]: Task File Auxiliary Status (R). This bit field defines the Channel X Task File Auxiliary Status
register.
• Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
Channel X Read Ahead Data
Address Offset: 8CH / CCH / 28CH / 2CCH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Read Ahead Data
This register defines the read ahead data port for PIO transfers on Channel X in the SiI3114. This register can be
accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this
register must be zero-aligned.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
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