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SII3114CTU 参数 Datasheet PDF下载

SII3114CTU图片预览
型号: SII3114CTU
PDF下载: 下载PDF文件 查看货源
内容描述: PCI串行ATA控制器 [PCI to Serial ATA Controller]
分类和应用: 外围集成电路控制器PC时钟
文件页数/大小: 127 页 / 559 K
品牌: SILICONIMAGE [ Silicon image ]
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SiI3114 PCI to Serial ATA Controller  
Data Sheet  
Silicon Image, Inc.  
FIFO Pointers1– Channel X  
Address Offset: 68H / 78H / 268H / 278H  
Access Type: Read Only  
Reset Value: 0x0000_0000  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
FIFO Byte 1 Wr Pointer  
FIFO Byte 1 Rd Pointer  
FIFO Byte 0 Wr Pointer  
FIFO Byte 0 Rd Pointer  
This register provides visibility into the data FIFO for Channel X in the SiI3114. The data FIFO is organized as a  
four byte-wide x 64 deep memory array. There are separate write and read pointers for each of the byte slices.  
This register is used for hardware debugging purposes only. The register bits are defined below.  
Bit [31:24]: FIFO Byte 1 Wr Pointer (R). This bit field provides the write pointer for Byte 1.  
Bit [23:16]: FIFO Byte 1 Rd Pointer (R). This bit field provides the read pointer for Byte 1.  
Bit [15:08]: FIFO Byte 0 Wr Pointer (R). This bit field provides the write pointer for Byte 0.  
Bit [07:00]: FIFO Byte 0 Rd Pointer (R). This bit field provides the read pointer for Byte 0.  
FIFO Pointers2– Channel X  
Address Offset: 6CH / 7CH / 26CH / 27CH  
Access Type: Read Only  
Reset Value: 0x0000_0000  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
FIFO Byte 3 Wr Pointer  
FIFO Byte 3 Rd Pointer  
FIFO Byte 2 Wr Pointer  
FIFO Byte 2 Rd Pointer  
This register provides visibility into the data FIFO for Channel X in the SiI3114. The data FIFO is organized as a  
four byte-wide x 64 deep memory array. There are separate write and read pointers for each of the byte slices.  
This register is used for hardware debugging purposes only. The register bits are defined below.  
Bit [31:24]: FIFO Byte 3 Wr Pointer (R). This bit field provides the write pointer for Byte 3.  
Bit [23:16]: FIFO Byte 3 Rd Pointer (R). This bit field provides the read pointer for Byte 3.  
Bit [15:08]: FIFO Byte 2 Wr Pointer (R). This bit field provides the write pointer for Byte 2.  
Bit [07:00]: FIFO Byte 2 Rd Pointer (R). This bit field provides the read pointer for Byte 2.  
© 2007 Silicon Image, Inc.  
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SiI-DS-0103-D  
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