SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
• Bit [28]: Mem Error (R/W1C) – Memory Access Error. This bit set indicates that the EEPROM interface
logic detects three NAKs from the memory device (EEPROM most likely not present.)
• Bit [27]: Mem Init Done (R) – Memory Initialization Done. This bit set indicates that the memory
initialization sequence is done. The memory initialization sequence is activated upon the release of reset.
• Bit [26]: Mem Init (R) – Memory Initialized. This bit set indicates that the memory was initialized properly (a
correct data sequence was read from the EEPROM.)
• Bit [25]: Mem Access Start (R/W) – Memory Access Start. This bit is set to initiate an operation to
EEPROM memory. This bit is cleared when the operation is complete.
• Bit [24]: Mem Access Type (R/W) – Memory Access Type. This bit is set to define a read operation from
EEPROM memory. This bit is cleared to define a write operation to EEPROM memory.
• Bit [23:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [07:00]: Memory Address (R/W). This bit field is programmed with the address for an EEPROM
memory read or write access.
EEPROM Memory Data
Address Offset: 5CH
Access Type: Read/Write
Reset Value: 0x0000_00XX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for EEPROM memory interface in the SiI3114. The system writes to this
register for a write operation to EEPROM memory, and reads from this register on a read operation from
EEPROM memory. The register bits are defined below.
• Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [07:00]: Memory Data (R/W) – EEPROM Memory Data. This bit field is used for EEPROM write data on
a write operation, and returns the EEPROM read data on a read operation.
FIFO Port – Channel X
Address Offset: 60H / 70H / 260H / 270H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIFO Port
This register defines the direct access register for the FIFO port of Channel X in the SiI3114. This register is used
for hardware debugging purposes only. The system can read from or write to this register for direct access to the
data FIFO between the PCI bus and Channel X. While DMA is active, reading this register will be terminated with
Target-Abort.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
SILICONIMAGE [ Silicon image ]
