SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Data Transfer Mode – Channel 0/2
Address Offset: 80H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for Channel 0/2 in the SiI3114. The register bits are also mapped
to Base Address 5, Offset B4H. See “Data Transfer Mode – Channel X” section on page 66 for bit definitions.
Data Transfer Mode – Channel 1/3
Address Offset: 84H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for Channel 1/3 in the SiI3114. The register bits are also mapped
to Base Address 5, Offset F4H. See “Data Transfer Mode – Channel X” section on page 66 for bit definitions.
System Configuration Status – Command
Address Offset: 88H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the system configuration status and command register for the SiI3114. The register bits are
also mapped to Base Address 5, Offset 48H. See “System Configuration Status – Command” section on page 57
for bit definitions.
SiI-DS-0103-D
36
© 2007 Silicon Image, Inc.
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