SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
PLL VCO Bias
Pin Name: PLL_VCOBIAS
Pin Number: 4
Dedicated PLL analog pin for VCO bias. Refer to section 7.1 for PLL connections.
PLL Loop Filter
Pin Name: PLL_LOOPFLT
Pin Number: 5
Dedicated PLL analog input for off-chip loop filter. Refer to section 7.1 for PLL connections.
PLL Ground
Pin Name: PLL_GND
Pin Number: 6
Dedicated PLL Ground (Power supply reference). Refer to section 7.1 for PLL connections.
Test Mode
Pin Name: TEST_MODE
Pin Number: 7
This pin, in conjunction with other pins, enables various test functions within the device. This pin should tied to ground for
normal operation.
Power Supply
Pin Name(s): VDD
Pin Number(s): 16, 26, 36, 51, 61, 72, 87, 98, 108, 118, 128and144
Power Supply Input (3.3 volts +/- 10%)
IDE Configuration
Pin Names: JP
Pin Numbers: 80
IDE Configuration Jumper Pin.
JP Pin
CONFIGURATION
0
1
RAID Class, PCI Class Code = 010400h
IDE Class, PCI Class Code = 010185h
Table 3-2: ATA Configuration
This pin has an internal pull-up resistor, and if left unconnected, will default to ‘1’. Otherwise, tie this pin high (1,) or low (0) to
select the desired mode.
It is recommended that this pin to be tied to low (RAID Class) when Silicon Image drivers (RAID or Non-RAID) are used.
Base Address 5 Enable
Pin Name: BA5_EN
Pin Number: 139
Base Address 5 Enable Jumper Pin.
BA5_EN Pin
CONFIGURATION
Base Address 5 Disabled ( Note 1)
Base Address 5 Enabled
0
1
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
30
SILICONIMAGE [ Silicon image ]
