SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Pin Number: 113
PCI_PAR is even parity across PCI_AD[31:0] and PCI_CBE[3:0]_N. Parity generation is required by all PCI agents. PCI_PAR
is stable and valid one clock after the address phase. For data phases PCI_PAR is stable and valid one clock after either
PCI_IRDY_N is asserted on a write transaction or PCI_TRDY_N is asserted on a read transaction. Once PCI_PAR is valid, it
remains valid until one clock after the completion of the current data phase. (PCI_PAR has the same timing as PCI_AD[31:0]
but delayed by one clock.)
PCI Request
Pin Name: PCI_REQ_N
Pin Number: 136
This signal indicates to the arbiter that this agent desires use of the PCI bus.
PCI Grant
Pin Name: PCI_GNT_N
Pin Number: 137
This signal indicates to the agent that access to the PCI bus has been granted. In response to a PCI request, this is a point-to-
point signal. Every master has its own PCI_GNT_N, which must be ignored while PCI_RST_N is asserted.
PCI Interrupt A
Pin Name: PCI_INTA_N
Pin Number: 138
Interrupt A is used to request an interrupt on the PCI bus. PCI_INTA_N is open collector and is an open drain output.
PCI Clock Signal
Pin Names: PCI_CLK
Pin Number: 140
Clock Signal provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals (except
PCI_RST_N, and PCI_INTA_N) are sampled on the rising edge of PCI_CLK. All other timing parameters are defined with
respect to this edge.
PCI Reset
Pin Name: PCI_RST_N
Pin Number: 141
PCI_RST_N is an active low input that is used to set the internal registers to their initial state. PCI_RST_N is typically the
system power-on reset signal as distributed on the PCI bus.
3.3.4 Miscellaneous I/O
Ground
Pin Name: VSS
Pin Number: 1, 17, 27, 37, 52, 62, 73, 88, 99, 109, 119, 129
Ground reference point to power supply.
PLL VDD
Pin Name: PLL_VDD
Pin Number: 2
Dedicated PLL Power supply (3.3 Volts +/- 10%). Refer to section 7.1 for PLL connections.
PLL Charge Pump Bias
Pin Name: PLL_CPBIAS
Pin Number: 3
Dedicated PLL analog pin for charge pump bias. Refer to section 7.1 for PLL connections.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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