SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
PCI Frame Cycle
Pin Name: PCI_FRAME_N
Pin Number: 104
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. PCI_FRAME_N is asserted
to indicate that a bus transaction is beginning. While PCI_FRAME_N is asserted, data transfers continue. When
PCI_FRAME_N is de-asserted, the transaction is in the final data phase or has completed.
PCI Initiator Ready
Pin Name: PCI_IRDY_N
Pin Number: 105
Initiator Ready indicates the initializing agent’s (bus master’s) ability to complete the current data phase of the transaction.
This signal is used with PCI_TRDY_N. A data phase is completed on any clock when both PCI_IRDY_N and PCI_TRDY_N
are sampled as asserted. Wait cycles are inserted until both PCI_IRDY_N and PCI_TRDY_N are asserted together.
PCI Target Ready
Pin Name: PCI_TRDY_N
Pin Number: 106
Target Ready indicates the target agent’s ability to complete the current data phase of the transaction. PCI_TRDY_N is used
with PCI_IRDY_N. A data phase is completed on any clock when both PCI_TRDY_N and PCI_IRDY_N are sampled asserted.
During a read, PCI_TRDY_N indicates that valid data is present on PCI_AD[31:0]. During a write, it indicates the target is
prepared to accept data.
PCI Device Select
Pin Name: PCI_DEVSEL_N
Pin Number: 107
Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access.
As an input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been selected.
PCI Stop
Pin Name: PCI_STOP_N
Pin Number: 110
PCI_STOP_N indicates the current target is requesting that the master stop the current transaction.
PCI Parity Error
Pin Name: PCI_PERR_N
Pin Number: 111
PCI_PERR_N indicates a data parity error between the current master and target on PCI. On a write transaction, the target
always signals data parity errors back to the master on PCI_PERR_N. On a read transaction, the master asserts
PCI_PERR_N to indicate to the system that an error was detected.
PCI System Error
Pin Name: PCI_SERR_N
Pin Number: 112
System Error is for reporting address parity errors, data parity errors on Special Cycle Command, or any other system error
where the result will be catastrophic. The PCI_SERR_N is a pure open drain and is actively driven for a single PCI clock by
the agent reporting the error. The assertion of PCI_SERR_N is synchronous to the clock and meets the setup and hold times
of all bused signals. However, the restoring of PCI_SERR_N to the de-asserted state is accomplished by a weak pull-up. Note
that if an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required.
PCI Parity
Pin Name: PCI_PAR
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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