Si8440/41/42/45
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si844xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
4.3
3.0
25
6.1
4.3
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
CMTI
V = V or 0 V
kV/µs
I
DD
Immunity at Logic Low Output
3
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
3
Enable to Data Tri-State
en2
3,4
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
11
SILICONIMAGE [ Silicon image ]
