Si3220/Si3225
If GCI mode is selected, the following pins must be tied
to the correct state to select one of eight subframe
timeslots in the GCI frame (described below). These
pins must remain in this state while the Dual ProSLIC is
operating. Selecting a particular subframe causes that
individual Dual ProSLIC device to transmit and receive
on the appropriate subframe in the GCI frame, which is
initiated by an FSYNC pulse. No further register settings
are needed to select which sub-frame a device uses,
and the sub-frame for a particular device cannot be
changed while in operation.
General Circuit Interface
The Dual ProSLIC devices also contain an alternate
communication interface to the SPI and PCM control
and data interface. The general circuit interface (GCI) is
used for the transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both four-wire interfaces and share the
same pins. The SPI control interface is not used as a
communication interface in the GCI mode but rather as
hard-wired channel selector pins. The selection
between PCM and GCI modes is performed out of reset
using the SDITHRU pin. Tables 43 and 44 illustrate how
to select the communication mode and how the pins are
used in each mode.
Table 45. GCI Mode Sub-Frame Selection
SDI SDO
CS
GCI Subframe 0 Selected
(Voice channels 1–2)
GCI Subframe 1 Selected
(Voice channels 3–4)
GCI Subframe 2 Selected
(Voice channels 5–6)
GCI Subframe 3 Selected
(Voice channels 7–8)
GCI Subframe 4 Selected
(Voice channels 9–10)
GCI Subframe 5 Selected
(Voice channels 11–12)
GCI Subframe 6 Selected
(Voice channels 13–14)
GCI Subframe 7 Selected
(Voice channels 15–16)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
Table 43. PCM or GCI Mode Selection
SDITHRU SCLK
Mode Selected
0
1
0
1
0
1
0
0
1
x
GCI Mode—1x PCLK (2.048 MHz)
0
0
1
GCI Mode—2x PCLK (4.096 MHz)
PCM Mode
Note: Values shown are the states of the pins at the rising
edge of RESET.
Table 44. Pin Functionality in PCM or GCI Mode
Pin Name
PCM Mode
GCI Mode
CS
SPI Chip Select
Channel Selector,
bit 0
SCLK
SDI
SPI Clock Input
PCLK Rate
Selector
SPI Serial Data Input Channel Selector,
bit 2
In GCI mode, the PCLK input requires either a
2.048 MHz or a 4.096 MHz clock signal, and the
FSYNC input requires an 8 kHz frame sync signal. The
overall unit of data used to communicate on the GCI
highway is a frame 125 µs in length. Each frame is
initiated by a pulse on the FSYNC pin whose rising
edge signifies the beginning of the next frame. In 2x
PCLK mode, the user sees twice as many PCLK cycles
during each 125 µs frame versus 1x PCLK mode. Each
frame consists of eight fixed timeslot subframes that are
assigned by the Sub-Frame Select pins as described
above (SDI, SDO, and CS). Within each sub-frame are
four channels (bytes) of data including two voice data
channels, B1 and B2, one Monitor channel, M, used for
initialization and setup of the device, and one Signaling
and Control channel, SC, used for communicating the
status of the device and initiating commands. Within the
SC channel are six Command/Indicate (C/I) bits and two
SDO
SPI Serial Data
Output
Channel Selector,
bit 1
SDITHRU SPI Data Throughput
pin for Daisy Chaining
Operation (Connects
to the SDI pin of the
PCM/GCI Mode
Selector
subsequent device in
the daisy chain)
FSYNC
PCM Frame Sync
GCI Frame Sync
Input
GCI Input Clock
Input
PCLK
DTX
DRX
PCM Input Clock
PCM Data Transmit GCI Data Transmit
PCM Data Receive GCI Data Receive
Note: This table denotes pin functionality after the rising
edge of RESET and mode selection.
Rev. 1.0
79
SILICONIMAGE [ Silicon image ]
