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SI3225-FQ 参数 Datasheet PDF下载

SI3225-FQ图片预览
型号: SI3225-FQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双PROSLIC®可编程CMOS SLIC / CODEC [DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC]
分类和应用: 电池电信集成电路
文件页数/大小: 108 页 / 1519 K
品牌: SILICONIMAGE [ Silicon image ]
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Si3220/Si3225  
CS  
SCLK  
SDI  
CONTROL  
ADDRESS  
Data [15:8]  
Data [7:0]  
SDO  
Figure 50. RAM Read Operation via a 16-Bit SPI Port  
PCM Interface  
The Dual ProSLIC devices contain  
a
flexible duration of the 8-bit PCM transmit. DTX returns to high-  
programmable interface for the transmission and impedance on the negative edge of PCLK during the  
reception of digital PCM samples. PCM data transfer is LSB or on the positive edge of PCLK following the LSB.  
controlled by the PCLK and FSYNC inputs, PCM Mode This is based on the setting of the PCMTRI bit of the  
Select, PCM Transmit Start Count (PCMTXHI/ PCM Mode Select register. Tristating on the negative  
PCMTXLO), and PCM Receive Start Count (PCMRXHI/ edge allows the transmission of data by multiple  
PCMRXLO) registers. The interface can be configured sources in adjacent timeslots without the risk of driver  
to support from 4 to 128 8-bit timeslots in each frame. contention. In addition to 8-bit data modes, a 16-bit  
This corresponds to PCLK frequencies of 256 kHz to mode is provided for testing. This mode can be  
8.192 MHz in power-of-2 increments. (768 kHz, activated via the PCMF bits of the PCM Mode Select  
1.536 MHz, and 1.544 MHz are also available for T1 register.  
Setting  
the  
PCMTXHI/PCMTXLO  
or  
and E1 support.) Timeslots for data transmission and PCMRXHI/PCMRXLO register greater than the number  
reception are independently configured with the of PCLK cycles in a sample period stops data  
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO. transmission because neither PCMTXHI/PCMTXLO nor  
Setting the correct starting point of the data configures PCMRXHI/PCMRXLO equal the PCLK count. Figures  
the part to support long FSYNC and short FSYNC 51–54 illustrate the usage of the PCM highway interface  
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time to adapt to common PCM standards.  
slots. DTX data is high-impedance except for the  
PCLK  
FSYNC  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
PCLK_CNT  
DRX  
MSB  
MSB  
LSB  
LSB  
DTX  
HI-Z  
HI-Z  
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)  
74  
Rev. 1.0