Si3220/Si3225
Note: Therefore, the RESET pin must be held low during
powerup and should only be released when both
PCLK and FSYNC signals are known to be stable.
64
--------------
=
Tsettle
fPCLK
VCO
28.672 MHz
PCLK
PFD
÷2
÷2
DIV M
PLL_MULT
RESET
Figure 40. PLL Frequency Synthesizer
Interrupt Logic
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0–IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-zero,
the INT pin remains asserted.
The Dual ProSLIC devices are capable of generating
interrupts for the following events:
ꢀ Loop current/ring ground detected
ꢀ Ring trip detected
ꢀ Ground Key detected
ꢀ Power alarm
ꢀ DTMF digit detected
ꢀ Active timer 1 expired
ꢀ Inactive timer 1 expired
SPI Control Interface
ꢀ Active timer 2 expired
The control interface to the Dual ProSLIC devices is a
4-wire SPI bus modeled after microcontroller and serial
peripheral devices. The interface consists of a clock,
SCLK, chip select, CS, serial data input, SDI, and serial
data output, SDO. In addition, the Dual ProSLIC devices
include a serial data through output (SDI_THRU) to
support daisy-chain operation of up to eight devices (up
to sixteen channels). Figure 41 illustrates the daisy-
chain connections. Note that the SDITHRU pin of the
last device in the chain must not be connected to
ꢀ Inactive timer 2 expired
ꢀ Ringing active timer expired
ꢀ Ringing inactive timer expired
ꢀ Pulse metering active timer expired
ꢀ Pulse metering inactive timer expired
ꢀ RAM address access complete
ꢀ Receive path modem tone detected
ꢀ Transmit path modem tone detected
The interface to the interrupt logic consists of six ground (SDITHRU = 0 indicated GCI mode). The device
registers. Four interrupt status registers (IRQ0–IRQ3) operates with both 8-bit and 16-bit SPI controllers. Each
contain 1 bit for each of the above interrupt functions. SPI operation consists of a control byte, an address
These bits are set when an interrupt is pending for the byte (of which only the seven LSBs are used internally),
associated resource. Three interrupt mask registers and either one or two data bytes depending on the width
(IRQEN1–IRQEN3) also contain 1 bit for each interrupt of the controller and whether the access is to an 8-bit
function. For interrupt mask registers, the bits are active register or 16-bit RAM address. Bytes are always
high. Refer to the appropriate functional description text transmitted MSB first. The variations of usage on this
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it ꢀ Continuous clocking. During continuous clocking,
signals an interrupt to the interrupt control block. The the data transfers are controlled by the assertion of
four-wire interface are as follows:
68
Rev. 1.0
SILICONIMAGE [ Silicon image ]
