Si3220/Si3225
Table 14. Switching Characteristics—GCI Highway Serial Interface
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
1
Test
Parameter
Symbol
Min
Typ
Max
Units
Conditions
PCLK Period (2.048 MHz PCLK Mode)
PCLK Period (4.096 MHz PCLK Mode)
FSYNC Period
t
t
—
—
—
40
488
244
125
50
—
—
—
60
ns
ns
µs
%
p
p
2
t
fs
PCLK Duty Cycle Tolerance
t
dty
FSYNC Jitter Tolerance
t
—
—
±120
ns
jitter
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tristate
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
FSYNC Pulse Width
t
t
f
—
—
—
—
—
25
20
25
20
—
—
—
—
—
—
—
—
—
—
25
25
20
20
20
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
r
t
t
t
t
t
t
t
t
d1
d2
d3
3
su1
h1
su2
h2
t /2
p
wfs
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and
fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
tr
tf
tp
PCLK
th1
tsu1
tfs
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td2
td3
Frame 0,
Bit 0
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
Rev. 1.0
19
SILICONIMAGE [ Silicon image ]
