Preliminary
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Alternate
LOCATION
Functionality
US1_CLK
0
1
2
3
PC15
PC14
4
5
6
Description
PB7
PF0
PF1
USART1 clock input / output.
US1_CS
PB8
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PD6
PD7
PD6
PD7
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
PC0
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32ZG110 is shown in Table 4.3 (p. 51). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA0
PB14 PB13
PB11
-
PB8
PB7
-
-
-
-
-
-
PC1
-
-
PC0
-
PC15 PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD7
PD6
-
-
-
-
-
PE13 PE12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF2
PF1
PF0
www.silabs.com
2013-10-09 - EFM32ZG110FXX - d0064_Rev0.60
51
SILICONIMAGE [ Silicon image ]
