Preliminary
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2.2 Configuration Summary
The features of the EFM32ZG108 is a subset of the feature set described in the EFM32ZG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M0+
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA and I2S
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
WDOG
PRS
NA
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
PCNT0
ACMP0
VCMP
GPIO
Full configuration, 16-bit count register PCNT0_S[1:0]
Full configuration
Full configuration
17 pins
ACMP0_CH[1:0], ACMP0_O
NA
Available pins are shown in
Table 4.3 (p. 37)
2.3 Memory Map
The EFM32ZG108 memory map is shown in Figure 2.2 (p. 7), with RAM and Flash sizes for the
largest memory configuration.
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2013-10-09 - EFM32ZG108FXX - d0063_Rev0.60
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